✅ 1. led blink 1s

module led_blink_1s(
    input clk,
    input reset,
    output reg [7:0] led
    );

    reg clk_1Hz;
    reg [26:0] count;

    // 1Hz clock 생성 
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            count <= 0;
            clk_1Hz <= 0;
        end
        else begin
            if(count == 49999999) begin
                count <= 0;
                clk_1Hz <= ~clk_1Hz;
            end
            else begin
                count <= count + 1;
            end
        end
    end

    always @(posedge clk_1Hz or posedge reset) begin
        if(reset) begin
            led <= 8'b00000000;
        end
        else begin
            led <= ~led;
        end
    end

endmodule

✅ 2. led shift Right

module led_shift_R (
    input clk,
    input reset,
    output reg [7:0] led
    );

    reg clk_1Hz;
    reg [26:0] count;

    // 1Hz clock 생성 
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            count <= 0;
            clk_1Hz <= 0;
        end
        else begin
            if(count == 49999999) begin
                count <= 0;
                clk_1Hz <= ~clk_1Hz;
            end
            else begin
                count <= count + 1;
            end
        end
    end

    // 오른쪽부터 shift
    always @(posedge clk_1Hz or posedge reset) begin
        if(reset) begin
            led <= 8'b00000001;
        end
        else begin
            led <= (led == 8'b10000000) ? 8'b00000001 : led << 1;
        end
    end
    
endmodule

✅ 3. led shift Light

module led_shift_L (
    input clk,
    input reset,
    output reg [7:0] led
    );

    reg clk_1Hz;
    reg [26:0] count;

    // 1Hz clock 생성 
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            count <= 0;
            clk_1Hz <= 0;
        end
        else begin
            if(count == 49999999) begin
                count <= 0;
                clk_1Hz <= ~clk_1Hz;
            end
            else begin
                count <= count + 1;
            end
        end
    end

    // 왼쪽부터 shift 
    always @(posedge clk_1Hz or posedge reset) begin
        if(reset) begin
            led <= 8'b10000000;
        end
        else begin
            led <= (led == 8'b00000001) ? 8'b10000000 : led >> 1;
        end
    end
    
endmodule

✅ 4. led shift Right & Left

module led_shift_RL (
    input clk,
    input reset,
    output reg [7:0] led
    );

    reg clk_1Hz;
    reg [26:0] count;
    reg dir;

    // 1Hz clock 생성 
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            count <= 0;
            clk_1Hz <= 0;
        end
        else begin
            if(count == 49999999) begin
                count <= 0;
                clk_1Hz <= ~clk_1Hz;
            end
            else begin
                count <= count + 1;
            end
        end
    end

		// LED 제어
    always @(posedge clk_1Hz or posedge reset) begin
        if(reset) begin
            led <= 8'b00000001;
            dir <= 0;   // R -> L
        end else begin
            case (dir)
                0 : begin
                    if(led == 8'b10000000) begin
                        dir <= 1;   // 방향 전환 
                        led <= led >> 1;
                    end else begin
                        led <= led << 1;
                    end
                end
                1 : begin
                    if(led == 8'b00000001) begin
                        dir <= 0;
                        led <= led << 1;
                    end else begin
                        led <= led >> 1;
                    end
                end
            endcase
        end
    end    
    
endmodule

// LED 제어 이런식으로도 가능
always @(posedge clk_1Hz or posedge reset) begin
    if(reset) begin
        led <= 8'b00000001; // start right
        dir <= 0;           // move left
    end else begin
        if(dir == 0) begin  
            if(led == 8'b10000000)
                dir <= 1;
            else
                led <= led >> 1;
        end else begin
            if(led == 8'b00000001)
                dir <= 0;
            else
                led <= led << 1; 
        end
    end
end

✅ 4. led ping pong

// left_s, right_s 3bit로 잡은 이유 -> 표현해야 할 숫자 범위는 0 ~ 7까지 
// 즉 2^3 = 8 => 3비트 필요
module led_ping_pong (
    input clk,
    input reset,
    output reg [7:0] led
    );

    reg clk_1Hz;
    reg [26:0] count;

    reg [2:0] left_s;
    reg [2:0] right_s;
    reg dir;

    // 1Hz clock 생성 
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            count <= 0;
            clk_1Hz <= 0;
        end
        else begin
            if(count == 49999999) begin
                count <= 0;
                clk_1Hz <= ~clk_1Hz;
            end
            else begin
                count <= count + 1;
            end
        end
    end

    always @(posedge clk_1Hz or posedge reset) begin
        if (reset) begin
            led <= 8'b10000001;
            left_s <= 0;
            right_s <= 7;
            dir <= 0; // 안쪽으로 시작
        end else begin
            // LED 초기화
            led <= 8'b00000000;
            // 두 위치 켜기
            led[left_s] <= 1'b1;
            led[right_s] <= 1'b1;

            // 방향에 따라 위치 업데이트
            if (dir == 0) begin
                // 안쪽으로 이동
                if (left_s < 3)
                    left_s <= left_s + 1;
                else
                    dir <= 1;  // 중앙 도달 → 반대 방향
                if (right_s > 4)
                    right_s <= right_s - 1;
            end else begin
                // 바깥쪽으로 이동
                if (left_s > 0)
                    left_s <= left_s - 1;
                else
                    dir <= 0;  // 양끝 도달 → 다시 안쪽
                if (right_s < 7)
                    right_s <= right_s + 1;
            end
        end
    end
    
endmodule

✅ 5. button led

module button_led(
    input clk,
    input reset,
    input btn_L,
    input btn_R,
    output reg [7:0] led
    );

    always @(posedge clk or posedge reset) begin
        if(reset) begin
            led <= 8'b00000000;
        end
        else begin
            if(btn_L)
                led <= 8'b00000000;
            else if(btn_R)
                led <= 8'b11111111;
        end
    end
endmodule

✅ 6. button deboucne

// button debounce
module debounce (
    input clk,
    input reset,
    input noise_btn,
    output reg clean_btn
);

    reg [16:0] cnt;
    reg btn_sync_0; 
    reg btn_sync_1;
    reg btn_state;

    // 2단 동기화
    always @(posedge clk) begin
        btn_sync_0 <= noise_btn;
        btn_sync_1 <= btn_sync_0;
    end

    // 디바운스 로직
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            cnt <= 0;
            btn_state <= 0;
            clean_btn <= 0;
        end else begin
            if (btn_sync_1 == btn_state) begin
                cnt <= 0;           // 입력이 이전 상태와 같으면: 안정된 상태 -> 카운터 리셋
            end else begin
                cnt <= cnt + 1;     // 이전상태와 다르면 카운트 증가

                if (cnt >= 100000) begin  // 1ms 유지 확인
                    btn_state <= btn_sync_1;
                    clean_btn <= btn_sync_1;
                    cnt <= 0;
                end
            end
        end
    end
endmodule